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A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips.

, , , and . VLSI Design, (2017)

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Low-power memory repair for high defect densities., and . IOLTS, page 171-173. IEEE, (2015)Rout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs., , , and . ETS, page 1-6. IEEE, (2017)Design of Static CMOS Self-Checking Circuits using Built-In Current Sensing., , and . FTCS, page 104-111. IEEE Computer Society, (1992)Fault-Secure Parity Prediction Booth Multipliers., and . IEEE Des. Test Comput., 16 (3): 90-101 (1999)Embedded Robustness IPs for Transient-Error-Free ICs., , and . IEEE Des. Test Comput., 19 (3): 56-70 (2002)Iterative Diagnosis Approach for ECC-Based Memory Repair., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (2): 464-477 (2020)Towards a holistic CAD platform for nanotechnologies., and . Microelectron. J., 39 (8): 1032-1040 (2008)Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip., , , , , and . Microprocess. Microsystems, 38 (6): 620-635 (2014)Programmable memory BIST., , , and . ITC, page 10. IEEE Computer Society, (2005)Congestion-Aware Adaptive Routing in 2D-Mesh Multicores., , and . NCA, page 50-58. IEEE Computer Society, (2014)