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A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration., , and . MCSoC, page 32-37. IEEE, (2019)Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel., and . CANDAR Workshops, page 280-284. IEEE, (2019)Foreword.. IEICE Trans. Inf. Syst., 95-D (12): 2749 (2012)Geyser., , , , , and . Handbook of Energy-Aware and Green Computing, Chapman and Hall/CRC, (2012)A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs., , , and . IEICE Trans. Inf. Syst., 90-D (12): 1914-1922 (2007)A Leakage Efficient Instruction TLB Design for Embedded Processors., , , , , and . IEICE Trans. Inf. Syst., 94-D (8): 1565-1574 (2011)Proxy Responses by FPGA-Based Switch for MapReduce Stragglers., , , and . IEICE Trans. Inf. Syst., 101-D (9): 2258-2268 (2018)GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures., , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (11): 2383-2396 (2020)A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures., and . IEICE Trans. Inf. Syst., 102-D (7): 1247-1256 (2019)A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing., , , , , , and . IEICE Trans. Inf. Syst., 100-D (8): 1798-1806 (2017)