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QoS policies and architecture for cache/memory in CMP platforms., , , , , , , , и . SIGMETRICS, стр. 25-36. ACM, (2007)Reducing cache and TLB power by exploiting memory region and privilege level semantics., , , , , , и . J. Syst. Archit., 59 (6): 279-295 (2013)Rate-based QoS techniques for cache/memory in CMP platforms., , , , , и . ICS, стр. 479-488. ACM, (2009)Comparing the memory system performance of the HP V-class and SGI Origin 2000 multiprocessors using microbenchmarks and scientific applications., , , и . International Conference on Supercomputing, стр. 339-347. ACM, (1999)Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors., , и . IPDPS, стр. 721-728. IEEE Computer Society, (2000)RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization., , , , , , , , , и 1 other автор(ы). NetSoft, стр. 335-343. IEEE, (2020)SpliceNP: a TCP splicer using a network processor., , , и . ANCS, стр. 135-143. ACM, (2005)Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family., , , , , , и . HPCA, стр. 657-668. IEEE Computer Society, (2016)Hardware Support for Bulk Data Movement in Server Platforms., , , , и . ICCD, стр. 53-60. IEEE Computer Society, (2005)Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation., , , , , , , , , и . ISQED, стр. 547-552. IEEE, (2021)