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Disambiguation of "Gomony, Manil Dev"

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A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems.

, , , , and . IEEE Trans. Computers, 66 (2): 212-225 (2017)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Vlad Manilici

Flow-based routing in community networks. TU Berlin, (2009)

Arvind Dev

Efraín Manilla-Pérez

Daulat Ram Dev

Nagendu Bikar Dev

 

Other publications of authors with the same name

The Hardware Foundation of 6G: The NEW-6G Approach., , , , , , , , , and 1 other author(s). EuCNC, page 423-428. IEEE, (2022)PetaOps/W edge-AI $\mu$ Processors: Myth or reality?, , , , , , , , , and 18 other author(s). DATE, page 1-6. IEEE, (2023)BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC., , , , and . ICCD, page 78-85. IEEE, (2023)BrainTTA: A 35 fJ/op Compiler Programmable Mixed-Precision Transport-Triggered NN SoC., , , , and . CoRR, (2022)THOR - A Neuromorphic Processor with 7.29G TSOP$^2$/mm$^2$Js Energy-Throughput Efficiency., , , , and . CoRR, (2022)Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems., , and . DATE, page 1-6. European Design and Automation Association, (2014)Reconfigurable Signal Processing and DSP Hardware Generator for 5G and Beyond Transmitters., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 32 (1): 4-15 (January 2024)Virtual execution platforms for mixed-time-criticality systems: the CompSOC architecture and design flow., , , , , , , , , and 2 other author(s). SIGBED Rev., 10 (3): 23-34 (2013)Dilate-Invariant Temporal Convolutional Network for Real-Time Edge Applications., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (3): 1210-1220 (2022)Dependability of Future Edge-AI Processors: Pandora's Box., , , , , , , , , and 3 other author(s). ETS, page 1-6. IEEE, (2023)