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Retiming Verification Using Sequential Equivalence Checking.

, and . MTV, page 138-142. IEEE Computer Society, (2005)

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Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams., and . IEEE Trans. Computers, 35 (4): 375-379 (1986)Verification and Validation of Complex Digital Systems: An Industrial Perspective., and . ISQED, page 11-12. IEEE Computer Society, (2001)Efficient Algorithmic Circuit Verification Using Indexed BDDs., , , , and . FTCS, page 266-275. IEEE Computer Society, (1994)Design rewiring based on diagnosis techniques., , and . ASP-DAC, page 479-484. ACM, (2001)Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification., , , and . IEEE Des. Test, 34 (5): 5-6 (2017)Functional Testing of Semiconductor Random Access Memories., and . ACM Comput. Surv., 15 (3): 175-198 (1983)Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays., and . J. Electron. Test., 13 (2): 121-135 (1998)Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory., , , , , , , , , and 47 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 27 (2): 253-280 (2019)A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPCTM microprocessor., , and . CICC, page 71-74. IEEE, (2000)Oscillation Ring Delay Test for High Performance Microprocessors., , , , and . J. Electron. Test., 16 (1-2): 147-155 (2000)