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Expressing logical and temporal conditions in simulation environments: TPDL*.

, , , and . Microprocessing and Microprogramming, 26 (4): 241-252 (1989)

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Interpolation with Guided Refinement: Revisiting incrementality in SAT-based unbounded model checking., , and . FMCAD, page 43-50. IEEE, (2014)Tightening BDD-based approximate reachability with SAT-based clause generalization∗., , , and . DATE, page 1-6. European Design and Automation Association, (2014)Cross-fertilizing FSM verification techniques and sequential diagnosis., , , , and . EURO-DAC, page 306-311. IEEE Computer Society Press, (1992)SAT solver management strategies in IC3: an experimental approach., , , , and . Formal Methods Syst. Des., 50 (1): 39-74 (2017)TPDL: Extended Temporal Profile Description Language., , , and . Softw. Pract. Exp., 21 (4): 355-374 (1991)Symbolic traversals of data paths with auxiliary variables., , and . Great Lakes Symposium on VLSI, page 93-96. IEEE, (1994)Thread-based multi-engine model checking for multicore platforms., , and . ACM Trans. Design Autom. Electr. Syst., 18 (3): 36:1-36:28 (2013)Verification and synthesis of counters based on symbolic techniques., , , and . ED&TC, page 176-181. IEEE Computer Society, (1997)Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking., , , , and . BMC@CAV, volume 119 of Electronic Notes in Theoretical Computer Science, page 33-49. Elsevier, (2004)A BMC-formulation for the scheduling problem in highly constrained hardware Systems., , , , , and . BMC@CAV, volume 89 of Electronic Notes in Theoretical Computer Science, page 623-638. Elsevier, (2003)