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III-V HBTs on 300 mm Si substrates using merged nano-ridges and its application in the study of impact of defects on DC and RF performance.

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Impact of slow and fast oxide traps on In0.53Ga0.47As device operation studied using CET maps., , , , , , and . IRPS, page 5. IEEE, (2018)III-V HBTs on 300 mm Si substrates using merged nano-ridges and its application in the study of impact of defects on DC and RF performance., , , , , , , , , and 4 other author(s). ESSDERC, page 261-264. IEEE, (2022)Determination of energy and spatial distribution of oxide border traps in In0.53Ga0.47As MOS capacitors from capacitance-voltage characteristics measured at various temperatures., , , , , , , , , and 1 other author(s). Microelectron. Reliab., 54 (4): 746-754 (2014)The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices., , , , , , , , , and 2 other author(s). IRPS, page 5. IEEE, (2015)A defect characterization technique for the sidewall surface of Nano-ridge and Nanowire based Logic and RF technologies., , , , , , , , , and 1 other author(s). IRPS, page 1-5. IEEE, (2021)Beyond-Si materials and devices for more Moore and more than Moore applications., , , , , , , , , and 16 other author(s). ICICDT, page 1-5. IEEE, (2016)