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Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (2): 380-393 (2008)Depth-driven verification of simultaneous interfaces., , and . ASP-DAC, page 442-447. IEEE, (2006)Post-Silicon Validation of Multiprocessor Memory Consistency., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (6): 1027-1037 (2015)An Effective Verification Solution for Modern Microprocessors.. University of Michigan, USA, (2008)Testudo: Heavyweight security analysis via statistical sampling., , , , , , and . MICRO, page 117-128. IEEE Computer Society, (2008)Energy-efficient cache design using variable-strength error-correcting codes., , , , , and . ISCA, page 461-472. ACM, (2011)Automatic error diagnosis and correction for RTL designs., , , and . HLDVT, page 65-72. IEEE Computer Society, (2007)StressTest: an automatic approach to test generation via activity monitors., , and . DAC, page 783-788. ACM, (2005)Shielding against design flaws with field repairable control logic., , and . DAC, page 344-347. ACM, (2006)Dacota: Post-silicon validation of the memory subsystem in multi-core designs., , and . HPCA, page 405-416. IEEE Computer Society, (2009)