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Rank-aware cache replacement and write buffering to improve DRAM energy efficiency., and . ISLPED, page 383-388. ACM, (2010)DRAM Refresh Mechanisms, Penalties, and Trade-Offs., , , , and . IEEE Trans. Computers, 65 (1): 108-121 (2016)Energy-efficient cache design using variable-strength error-correcting codes., , , , , and . ISCA, page 461-472. ACM, (2011)Memory system characterization of deep learning workloads., and . MEMSYS, page 497-505. ACM, (2019)Reducing DRAM Refresh Overheads with Refresh-Access Parallelism., , , , , , and . CoRR, (2018)Trading Off Cache Capacity for Low-Voltage Operation., , , , , and . IEEE Micro, 29 (1): 96-103 (2009)Adaptive Cache Design to Enable Reliable Low-Voltage Operation., , , , and . IEEE Trans. Computers, 60 (1): 50-63 (2011)DaeMon: Architectural Support for Efficient Data Movement in Disaggregated Systems., , , , , , and . CoRR, (2023)Trading off Cache Capacity for Reliability to Enable Low Voltage Operation., , , , , and . ISCA, page 203-214. IEEE Computer Society, (2008)Improving DRAM Performance by Parallelizing Refreshes with Accesses., , , , , , and . CoRR, (2017)