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Disambiguation of "Al-Khalili, Asim J."

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Energy delay analysis of partial product reduction methods for parallel multiplier implementation.

, , and . ISLPED, page 201-204. IEEE, (1996)

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Nikos Asimopoulos

Ina Asim

Asim Lutfi

Asim Khan

Arzhang Khalili

 

Other publications of authors with the same name

New modulo decomposed residue-to-binary algorithm for general moduli sets., , and . ICASSP (5), page 141-144. IEEE, (2004)Integrated Power and Clock Distribution Network., and . IEEE Trans. Very Large Scale Integr. Syst., 21 (10): 1941-1945 (2013)Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures., , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (1): 29-41 (2012)Analysis of Resistive Open Defects in Drowsy SRAM Cells., , and . J. Electron. Test., 27 (2): 203-213 (2011)Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (10): 1637-1643 (2005)Delay analysis of CMOS gates using modified logical effort model., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (6): 937-947 (2005)Energy delay analysis of partial product reduction methods for parallel multiplier implementation., , and . ISLPED, page 201-204. IEEE, (1996)On the Design of Optimal Fault-Tolerant Systolic Array Architecures., , and . IPPS, page 352-357. IEEE Computer Society, (1991)Modulo deflation in (2n+1, 2n, 2n-1) converters., , and . ISCAS (2), page 429-432. IEEE, (2004)An interconnect-aware delay model for dynamic voltage scaling in NM technologies., , and . ACM Great Lakes Symposium on VLSI, page 45-50. ACM, (2009)