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Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration.

A. Ramanathan, G. Kalsi, S. Srinivasa, T. Chandran, K. Pillai, O. Omer, V. Narayanan, and S. Subramoney. MICRO, page 88-101. IEEE, (2020)

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Akshay Balsubramani

Akshay Wadia

Akshay Gupte

Ramanathan Palaniappan

Ramanathan Muruganathan

Other publications of authors with the same name

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.S. Srinivasa, A. Ramanathan, X. Li, W. Chen, F. Hsueh, C. Yang, C. Shen, J. Shieh, S. Gupta, M. Chang and 3 other author(s). ISLPED, page 34:1-34:6. ACM, (2018)FARM: A Flexible Accelerator for Recurrent and Memory Augmented Neural Networks.N. Challapalle, S. Rampalli, N. Jao, A. Ramanathan, J. Sampson, and V. Narayanan. J. Signal Process. Syst., 92 (11): 1247-1261 (2020)Achieving Crash Consistency by Employing Persistent L1 Cache.A. Ramanathan, S. Mahdizadeh-Shahri, Y. Xiao, and V. Narayanan. DATE, page 1407-1412. IEEE, (2022)Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration.A. Ramanathan, G. Kalsi, S. Srinivasa, T. Chandran, K. Pillai, O. Omer, V. Narayanan, and S. Subramoney. MICRO, page 88-101. IEEE, (2020)CAPE: A Content-Addressable Processing Engine.H. Caminal, K. Yang, S. Srinivasa, A. Ramanathan, K. Al-Hawaj, T. Wu, V. Narayanan, C. Batten, and J. Martínez. HPCA, page 557-569. IEEE, (2021)IMC-Sort: In-Memory Parallel Sorting Architecture using Hybrid Memory Cube.Z. Li, N. Challapalle, A. Ramanathan, and V. Narayanan. ACM Great Lakes Symposium on VLSI, page 45-50. ACM, (2020)Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation.S. Srinivasa, A. Ramanathan, J. Sundaram, D. Kurian, S. Gopal, N. Jain, A. Srinivasan, R. Iyer, V. Narayanan, and T. Karnik. ISQED, page 547-552. IEEE, (2021)Integrated CAM-RAM Functionality using Ferroelectric FETs.S. George, N. Jao, A. Ramanathan, X. Li, S. Gupta, J. Sampson, and V. Narayanan. ISQED, page 81-86. IEEE, (2020)Programmable Non-Volatile Memory Design Featuring Reconfigurable In-Memory Operations.N. Jao, A. Ramanathan, A. Sengupta, J. Sampson, and V. Narayanan. ISCAS, page 1-5. IEEE, (2019)Recent Advances in Compute-in-Memory Support for SRAM Using Monolithic 3-D Integration.Z. Zhang, X. Si, S. Srinivasa, A. Ramanathan, and M. Chang. IEEE Micro, 39 (6): 28-37 (2019)

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Disambiguation of "Ramanathan, Akshay Krishna"

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Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration.

Please choose a person to relate this publication to

Akshay Balsubramani

Akshay Wadia

Akshay Gupte

Ramanathan Palaniappan

Ramanathan Muruganathan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ramanathan, Akshay Krishna"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration.

Please choose a person to relate this publication to

Akshay Balsubramani

Akshay Wadia

Akshay Gupte

Ramanathan Palaniappan

Ramanathan Muruganathan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration.