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Disambiguation of "Srinivasa, Srivatsa"

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Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration.

, , , , , , , and . MICRO, page 88-101. IEEE, (2020)

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Srinivasa Marimganti

Srinivasa Thimmaiah

Srinivasa Subramaniam

Srinath Srinivasa

Sundaravaradan Srinivasa Rangachari

 

Other publications of authors with the same name

Recent Advances in Compute-in-Memory Support for SRAM Using Monolithic 3-D Integration., , , , and . IEEE Micro, 39 (6): 28-37 (2019)Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration., , , , , and . IEEE Micro, 39 (6): 8-15 (2019)Hardware implementation low power high speed FFT core., and . Int. Arab J. Inf. Technol., 6 (1): 1-6 (2009)Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration., , , , , , , and . MICRO, page 88-101. IEEE, (2020)CAPE: A Content-Addressable Processing Engine., , , , , , , , and . HPCA, page 557-569. IEEE, (2021)Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation., , , , , , , , , and . ISQED, page 547-552. IEEE, (2021)Cryogenic Memory Technologies., , , and . CoRR, (2021)Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems., , , , , , , , , and 1 other author(s). ISQED, page 1-4. IEEE, (2022)Emerging reconfigurable nanotechnologies: can they support future electronics?, , , , , , , and . ICCAD, page 13. ACM, (2018)On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (10): 1603-1613 (October 2023)