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Disambiguation of "Pekmestzi, Kiamal Z."

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Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility.

, , , and . AHS, page 346-353. IEEE Computer Society, (2008)

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Z Taufig

Bence Z Szalai

Leonardo Quevedo Z

Milorad Z Djordjevic

ir Z hid

 

Other publications of authors with the same name

On the design of modulo 2n±1 residue generators., , , and . VLSI-SoC, page 33-38. IEEE, (2013)A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework., , , , , and . PATMOS, volume 6448 of Lecture Notes in Computer Science, page 73-83. Springer, (2010)Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (4): 607-611 (2019)On the Diminished-1 Modulo 2n+1 Addition and Subtraction., , and . J. Circuits Syst. Comput., 29 (5): 2030005:1-2030005:14 (2020)Efficient support vector machines implementation on Intel/Movidius Myriad 2., , , , , and . MOCAST, page 1-4. IEEE, (2018)A bit-interleaved systolic architecture for a high-speed RSA system., and . Integr., 30 (2): 169-175 (2001)VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (6): 1204-1208 (2018)Pipelined array-based FIR filter folding., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (1): 108-118 (2005)Efficient serial and parallel implementation of programmable fir filters based on the merging technique., , and . EUSIPCO, page 1-5. IEEE, (2008)A segmentation-based BISR scheme., , , , and . ASP-DAC, page 652-657. IEEE, (2014)