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A systematic approach for Failure Modes and Effects Analysis of System-On-Chips.

, and . IOLTS, page 187-188. IEEE Computer Society, (2007)

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Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508., , and . DATE, page 492-497. EDA Consortium, San Jose, CA, USA, (2007)Innovative Practices on In-System Test and Reliability of Memories., , , , , , , , , and 3 other author(s). VTS, page 1. IEEE, (2019)Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications., , , , and . ITC, page 1-6. IEEE, (2020)Advanced functional safety mechanisms for embedded memories and IPs in automotive SoCs., , , , , , and . ITC, page 1-6. IEEE, (2017)Advanced ECC solution for automotive SoCs., , , and . IOLTS, page 71-73. IEEE, (2017)A verification strategy for fault-detection and fault-tolerance circuits., , and . IOLTS, page 177-178. IEEE Computer Society, (2011)Advanced Uniformed Test Approach For Automotive SoCs., , , , , and . ITC, page 1-10. IEEE, (2018)Scrubbing and Partitioning for Protection of Memory Systems., and . IOLTS, page 195-196. IEEE Computer Society, (2005)Memory FIT Rate Mitigation Technique for Automotive SoCs., , , , , , , and . ITC, page 1-6. IEEE, (2019)A systematic approach for Failure Modes and Effects Analysis of System-On-Chips., and . IOLTS, page 187-188. IEEE Computer Society, (2007)