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Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion., , , , , and . J. Electron. Test., 29 (3): 289-299 (2013)DRAM Performance Sensor., , and . HCI (7), volume 13308 of Lecture Notes in Computer Science, page 510-521. Springer, (2022)A Zeta-CSC Converter Combination for Single-Input and Bipolar Output., , , , and . IECON, page 5721-5726. IEEE, (2019)From system level to defect-oriented test: a case study., , , , and . ETW, page 136-141. IEEE Computer Society, (1999)A distributed load scheduling mechanism for micro grids., , , and . SmartGridComm, page 278-283. IEEE, (2014)Time Management for Low-Power Design of Digital Systems., , , , , , and . J. Low Power Electron., 4 (3): 410-419 (2008)Lower VDD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing., , , , , , , , and . J. Low Power Electron., 7 (2): 185-198 (2011)On-Line BIST for Performance Failure Prediction Under NBTI-Induced Aging in Safety-Critical Applications., , , , and . J. Low Power Electron., 7 (4): 562-572 (2011)Signal Integrity Enhancement in Digital Circuits., , , , , , , and . IEEE Des. Test Comput., 25 (5): 452-461 (2008)The influence of clock-gating on NBTI-induced delay degradation., , , , , and . IOLTS, page 61-66. IEEE Computer Society, (2012)