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Disambiguation of "Freijedo, Judit"

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Time Management for Low-Power Design of Digital Systems.

, , , , , , and . J. Low Power Electron., 4 (3): 410-419 (2008)

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Iris Juditzki

Judit Mezey

Judit Balázs

Judit Horváth

Judit Jacob

 

Other publications of authors with the same name

Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems., , , , , and . J. Low Power Electron., 4 (3): 385-391 (2008)Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance., , , , , , , and . J. Low Power Electron., 6 (2): 339-349 (2010)Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits., , , , , and . J. Electron. Test., 28 (4): 421-434 (2012)Aging monitoring with local sensors in FPGA-based designs., , , , , , , , and . FPL, page 1-4. IEEE, (2013)Lower VDD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing., , , , , , , , and . J. Low Power Electron., 7 (2): 185-198 (2011)Time Management for Low-Power Design of Digital Systems., , , , , , and . J. Low Power Electron., 4 (3): 410-419 (2008)Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment., , , , , , , , , and 5 other author(s). LATW, page 1-6. IEEE, (2009)Performance Failure Prediction Using Built-In Delay Sensors in FPGAs., , , , , , , , and . FPL, page 301-304. IEEE Computer Society, (2011)Modeling the effect of process variations on the timing response of nanometer digital circuits., , , , , and . LATW, page 1-5. IEEE, (2011)Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects., , , , , , , and . LATW, page 1-7. IEEE, (2011)