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Disambiguation of "Lee, Jeong-Gun"

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Error-Resilient Inference with an Error-Aware Activation Function in a Deep Neural Network.

, and . ICEIC, page 1-4. IEEE, (2024)

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Jeong-Hoon Lee

Yoo-Jeong Lee

Eun-Jeong Lee

Jeong-Keun Lee

Jeong-Hoon Lee

 

Other publications of authors with the same name

Procedural Constraints in the Extended RBAC and the Coloured Petri Net Modeling., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (1): 327-330 (2005)A Carry Chain-Based ADMFC Design on an FPGA for EMI Reduction and Noise Compensation., , and . Journal of Circuits, Systems, and Computers, 28 (1): 1950018:1-1950018:23 (2019)Analysis of Clock Scheduling in Frequency Domain for Digital Switching Noise Suppressions., , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (9): 1685-1698 (2018)In-Situ Timing Error Predictor-Based Two-Cycle Adaptive Frequency Scaling System on an FPGA., , and . J. Circuits Syst. Comput., 29 (6): 2050098:1-2050098:22 (2020)Embedding High-Performance Synchronous Routers to Asynchronous Network on Chip., and . CDES, page 124-128. CSREA Press, (2008)Data Deduplication System for Supporting Multi-mode., , , , and . ACIIDS (1), volume 6591 of Lecture Notes in Computer Science, page 78-87. Springer, (2011)Sleep Stage Classification for Inter-institutional Transfer Learning., , , , and . ICTC, page 1797-1800. IEEE, (2021)Entropy-Based Model Generalization for Sleep Stage Classification., , , , and . ICTC, page 2213-2216. IEEE, (2022)472MHz throughput asynchronous FIFO design on a Virtex-5 FPGA device., , , and . IEICE Electron. Express, 8 (9): 676-683 (2011)High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion., , , , , and . ACM Great Lakes Symposium on VLSI, page 152-155. ACM, (2005)