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Disambiguation of "Curran, Brian W."

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Design of the Power6 Microprocessor.

, , , , , , , , , , , , , , , , and . ISSCC, page 96-97. IEEE, (2007)

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Brian Curran

Declan Curran

Rolf-Walter Briant

Benoît Briand

Christopher Curran

 

Other publications of authors with the same name

Design of the Power6 Microprocessor., , , , , , , , , and 7 other author(s). ISSCC, page 96-97. IEEE, (2007)IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology., , , , , , , , , and . IBM J. Res. Dev., 46 (4-5): 631- (2002)Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor., , , , , , , , , and 1 other author(s). IBM J. Res. Dev., 41 (4&5): 489-504 (1997)Design methodology for the S/390 Parallel Enterprise Server G4 microprocessors., , , , , , , , and . IBM J. Res. Dev., 41 (4&5): 515-548 (1997)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference., , , , , , , , , and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)Power-constrained high-frequency circuits for the IBM POWER6 microprocessor., , , , , , and . IBM J. Res. Dev., 51 (6): 715-732 (2007)RaPiD: AI Accelerator for Ultra-low Precision Training and Inference., , , , , , , , , and 44 other author(s). ISCA, page 153-166. IEEE, (2021)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference., , , , , , , , , and 33 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Deep submicron design techniques for the 500 MHz IBM S/390 G5 custom microprocessor., , , , , , , , , and 2 other author(s). ICCD, page 258-263. IEEE Computer Society, (1998)High-Performance CMOS Circuit Techniques for the G-4 S/390 Microprocessor., , , and . ICCD, page 247-252. IEEE Computer Society, (1997)