( en | de | ru )

 

Disambiguation of "Mittal, Rajesh"

Author of the publication

copydeleteadd this publication to your clipboard
Systematic approach for trim test time optimization: Case study on a multi-core RF SOC.

, , and . ITC, page 1-9. IEEE Computer Society, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Rupal Mittal

Ankit Mittal

Arpit Mittal

Rajesh Saiju

Hybrid Power System Modelling - Simulation and Energy Management Unit Development. Uni Kassel, (2008)

Manish Mittal

 

Other publications of authors with the same name

Towards adaptive test of multi-core RF SoCs., , , , , and . DATE, page 743-748. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation., , , , and . VTS, page 154-159. IEEE Computer Society, (2011)Test time reduction using parallel RF test techniques., , and . VTS, page 40. IEEE Computer Society, (2010)Tutorial T10: Post - Silicon Validation, Debug and Diagnosis., , , , , and . VLSI Design, IEEE Computer Society, (2013)DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2011)Systematic approach for trim test time optimization: Case study on a multi-core RF SOC., , and . ITC, page 1-9. IEEE Computer Society, (2014)Towards Single Pin Scan for Extremely Low Pin Count Test., , , and . VLSID, page 97-102. IEEE Computer Society, (2018)Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system., , , , , , , , , and 1 other author(s). DATE, page 551-554. IEEE, (2011)