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Disambiguation of "Kameyama, Michitaka"

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Architecture of a high-performance stereo vision VLSI processor.

, , and . Adv. Robotics, 14 (5): 329-332 (2000)

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Michitaka Ota

Shin'ichi Kameyama

 

Other publications of authors with the same name

A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment., and . APCCAS, page 1803-1806. IEEE, (2006)Interconnection-Free Biomolecular Computing., , and . Computer, 25 (11): 41-50 (1992)Low-power multiple-valued current-mode integrated circuit with current-source control and its application., , and . ASP-DAC, page 413-418. IEEE, (1997)An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture., , , and . ASP-DAC, page 89-90. IEEE, (2011)Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic., , and . J. Multiple Valued Log. Soft Comput., 11 (5-6): 619-632 (2005)Reversible, Information-Preserving Logic and Its Application., , , and . J. Multiple Valued Log. Soft Comput., 23 (3-4): 379-406 (2014)Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures., , , and . J. Multiple Valued Log. Soft Comput., 20 (5-6): 595-623 (2013)Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access., , and . IEICE Trans. Inf. Syst., 88-D (7): 1486-1491 (2005)Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits., and . IEICE Trans. Inf. Syst., 93-D (8): 2126-2133 (2010)Foreword.. IEICE Trans. Inf. Syst., 93-D (8): 2025 (2010)