From post

копировать удалить добавить публикацию в буфер
Запись сообщества
посмотреть историю данной записи
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators.

A. Paul, S. Park, D. Somasekhar, Y. Kim, N. Borkar, U. Karpuzcu, и C. Kim. IEEE Trans. Very Large Scale Integr. Syst., 24 (12): 3468-3476 (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Milind Borkar

Sirin Nitinawarat

Nitin Nangare

Nitin Suresh

Sachin Borkar

Другие публикации лиц с тем же именем

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS.S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, P. Iyer, A. Singh, T. Jacob и 4 other автор(ы). ISSCC, стр. 98-589. IEEE, (2007)A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS.P. Salihundam, S. Jain, T. Jacob, S. Kumar, V. Erraguntla, Y. Hoskote, S. Vangal, G. Ruhl, и N. Borkar. IEEE J. Solid State Circuits, 46 (4): 757-766 (2011)Design Challenges in Sub-100nm High Performance Microprocessors.S. Narendra, V. Erraguntla, J. Tschanz, и N. Borkar. VLSI Design, стр. 15-17. IEEE Computer Society, (2004)System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators.A. Paul, S. Park, D. Somasekhar, Y. Kim, N. Borkar, U. Karpuzcu, и C. Kim. IEEE Trans. Very Large Scale Integr. Syst., 24 (12): 3468-3476 (2016)5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS.S. Vangal, M. Anders, N. Borkar, E. Seligman, V. Govindarajulu, V. Erraguntla, H. Wilson, A. Pangal, V. Veeramachaneni, J. Tschanz и 12 other автор(ы). IEEE J. Solid State Circuits, 37 (11): 1421-1432 (2002)Resiliency for many-core system on a chip.T. Karnik, J. Tschanz, N. Borkar, J. Howard, S. Vangal, V. De, и S. Borkar. ASP-DAC, стр. 388-389. IEEE, (2014)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS.S. Jain, S. Khare, S. Yada, V. Ambili, P. Salihundam, S. Ramani, S. Muthukumar, M. Srinivasan, A. Kumar, S. Kumar и 11 other автор(ы). ISSCC, стр. 66-68. IEEE, (2012)An IA-32 processor with a wide voltage operating range in 32nm CMOS.G. Ruhl, S. Dighe, S. Jain, S. Khare, S. Yada, V. Ambili, P. Salihundam, S. Ramani, S. Muthukumar, M. Srinivasan и 9 other автор(ы). Hot Chips Symposium, стр. 1-37. IEEE, (2012)A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip.P. Salihundam, M. Khan, S. Jain, Y. Hoskote, S. Yada, S. Kumar, V. Erraguntla, S. Vangal, и N. Borkar. VLSI Design, стр. 292-297. IEEE Computer Society, (2012)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.S. Dighe, S. Vangal, P. Aseron, S. Kumar, T. Jacob, K. Bowman, J. Howard, J. Tschanz, V. Erraguntla, N. Borkar и 2 other автор(ы). ISSCC, стр. 174-175. IEEE, (2010)

BibSonomy

Disambiguation