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Disambiguation of "Borkar, Nitin"

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Design Challenges in Sub-100nm High Performance Microprocessors.

, , , and . VLSI Design, page 15-17. IEEE Computer Society, (2004)

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Milind Borkar

Sirin Nitinawarat

Nitin Nangare

Nitin Suresh

Sachin Borkar

 

Other publications of authors with the same name

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 98-589. IEEE, (2007)A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 757-766 (2011)System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (12): 3468-3476 (2016)Design Challenges in Sub-100nm High Performance Microprocessors., , , and . VLSI Design, page 15-17. IEEE Computer Society, (2004)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , and 11 other author(s). ISSCC, page 66-68. IEEE, (2012)5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 37 (11): 1421-1432 (2002)An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 43 (1): 29-41 (2008)Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 44 (4): 1199-1208 (2009)A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization., , , and . IEEE J. Solid State Circuits, 41 (10): 2314-2323 (2006)Resiliency for many-core system on a chip., , , , , , and . ASP-DAC, page 388-389. IEEE, (2014)