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Test pattern generation to detect multiple faults in ROBDD based combinational circuits., , and . IOLTS, page 211-212. IEEE, (2017)A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan., , , and . ATS, page 25-30. IEEE Computer Society, (2015)Self-Checking FSM Design with Observing only FSM Outputs., and . IOLTW, page 153-154. IEEE Computer Society, (2000)ROBDD based path delay fault testable combinational circuit synthesis., , and . EWDTS, page 1-4. IEEE Computer Society, (2016)ROBDDs application for finding the shortest transfer sequence of sequential circuit or only revealing existence of this sequence without deriving the sequence itself., , and . EWDTS, page 1-4. IEEE Computer Society, (2016)Path delay faults and ENF., , , and . EWDTS, page 164-167. IEEE Computer Society, (2010)Selection of the state variables for partial enhanced scan techniques., , , and . EWDTS, page 285-290. IEEE Computer Society, (2011)Finding False Paths for Sequential Circuits Using Operations on ROBDDs., , and . IOLTS, page 240-242. IEEE, (2018)Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits., and . Autom. Remote. Control., 76 (4): 658-667 (2015)Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design., , , and . J. Electron. Test., 34 (1): 53-65 (2018)