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Fault-Tolerant Synchronous FSM Network Design for Path Delay Faults., , , and . EWDTS, page 1-4. IEEE, (2018)A fault-tolerant combinational circuit design., , and . EWDTS, page 1-4. IEEE Computer Society, (2015)Self-Checking FSM Design with Observing only FSM Outputs., and . IOLTW, page 153-154. IEEE Computer Society, (2000)Trojan circuits masking and debugging of combinational circuits with LUT insertion., and . AQTR, page 1-6. IEEE, (2018)Implementation by the special formula of an arbitrary subset of code words of (m, n)-code for designing a self-testing checker., and . EWDTS, page 255-258. IEEE Computer Society, (2011)Detection and masking of Trojan Circuits in sequential logic., , , and . EWDTS, page 1-4. IEEE Computer Society, (2017)Sequential Circuits Applicable for Detecting Different Types of Faults., , , and . IOLTW, page 44-. IEEE Computer Society, (2002)Self-checking synchronous FSM network design for path delay faults.. EWDTS, page 1-4. IEEE Computer Society, (2017)Testable combinational circuit design based on ZDD-implementation of ISOP Boolean function., and . EWDTS, page 171-174. IEEE Computer Society, (2010)Partially programmable circuit design., , , and . EWDTS, page 1-4. IEEE Computer Society, (2014)