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Anomaly Detection in Real-Time Multi-Threaded Processes Using Hardware Performance Counters.

, , and . IEEE Trans. Inf. Forensics Secur., (2020)

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Concurrent Error Detection Schemes for Involution Ciphers., , and . CHES, volume 3156 of Lecture Notes in Computer Science, page 400-412. Springer, (2004)Hardware and embedded security in the context of internet of things., , and . CyCAR@CCS, page 61-64. ACM, (2013)Power Optimization for Universal Hash Function Data Path Using Divide-and-Concatenate Technique., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (10): 1763-1769 (2007)ASSURE: RTL Locking Against an Untrusted Foundry., , , , and . CoRR, (2020)Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (1): 2-15 (2015)Fuzzing+Hardware Performance Counters-Based Detection of Algorithm Subversion Attacks on Postquantum Signature Schemes., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (2): 384-396 (February 2023)Golden-Free Robust Age Estimation to Triage Recycled ICs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (9): 2839-2851 (September 2023)Robust Deep Learning for IC Test Problems., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (1): 183-195 (2022)Toward Secure and Trustworthy Cyberphysical Microfluidic Biochips., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (4): 589-603 (2019)On Improving the Security of Logic Locking., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (9): 1411-1424 (2016)