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Disambiguation of "Yoon, Jun-Sik"

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Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications.

, and . IEEE Access, (2020)

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Jun Sik Kim

Jun Jun Lu

Chang-Ju Yoon

Jeong-Weon Yoon

Deok Ryong Yoon

 

Other publications of authors with the same name

Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning., , , and . IEEE Access, (2021)Holistic Optimization of Trap Distribution for Performance/Reliability in 3-D NAND Flash Using Machine Learning., , , , , , , , and . IEEE Access, (2023)A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications., and . IEEE Access, (2020)Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes., , , , , and . IEEE Access, (2021)Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs., , and . IEEE Access, (2021)DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of Sub-3-nm Nanosheet Field-Effect Transistors., , , , , , and . IEEE Access, (2022)A Comparative Study on Front-Side, Buried and Back-Side Power Rail Topologies in 3nm Technology Node., , , and . ISLPED, page 1-6. IEEE, (2023)Neural Approach for Modeling and Optimizing Si-MOSFET Manufacturing., , , and . IEEE Access, (2020)Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node., , , , , , and . IEEE Access, (2019)Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application., , , and . IEEE Access, (2020)