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A contention-free domino logic for scaled-down CMOS technologies with ultra low threshold voltages.

, , and . ISCAS, page 748-751. IEEE, (2000)

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Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (5): 807-820 (2013)A contention-free domino logic for scaled-down CMOS technologies with ultra low threshold voltages., , and . ISCAS, page 748-751. IEEE, (2000)A DFM tool for analyzing lithography and stress effects on standard cells and critical path performance in 45nm digital designs., , , , and . IDT, page 13-17. IEEE, (2010)1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays., , , and . ASICON, page 12-15. IEEE, (2017)A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-Based Neuromorphic Systems., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (11): 3125-3137 (2017)A parametric DFM solution for analog circuits: Electrical driven hot spot detection, analysis and correction flow., , , , , , , and . SoCC, page 231-236. IEEE, (2011)Schematic-driven physical verification: Fully automated solution for analog IC design., , , , , , and . SoCC, page 260-264. IEEE, (2012)Effect of technology scaling on digital CMOS logic styles., , and . CICC, page 401-408. IEEE, (2000)8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM Design., , , and . ACM Great Lakes Symposium on VLSI, page 239-244. ACM, (2016)An electrical-aware parametric DFM solution for analog circuits., , , , , , , and . IDT, page 68-73. IEEE, (2011)