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Disambiguation of "Plana, Luis A."

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Understanding the interconnection network of SpiNNaker.

, , , , and . ICS, page 286-295. ACM, (2009)

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Juliana Plana Borrás

Lara Planas Paz

Werner Luis

Emmanuel Planas

Pia Luislampe

 

Other publications of authors with the same name

Adaptive admission control on the SpiNNaker MPSoC., , and . SoCC, page 243-246. IEEE, (2009)Performance-driven syntax-directed synthesis of asynchronous processors., , , , and . CASES, page 43-47. ACM, (2007)Architectural optimization for low-power nonpipelined asynchronous systems., and . IEEE Trans. Very Large Scale Integr. Syst., 6 (1): 56-65 (1998)Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (8): 763-767 (2016)An admission control system for QoS provision on a best-effort GALS interconnect., , , and . ACSD, page 200-207. IEEE, (2008)A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect., , , and . Fundam. Informaticae, 95 (1): 53-72 (2009)Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric., , , , , , , , , and 2 other author(s). Parallel Comput., 37 (8): 392-409 (2011)Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (8): 2973-2986 (2019)Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System., , , , and . HPCC-ICESS, page 1-8. IEEE Computer Society, (2012)An Investigation into the Security of Self-Timed Circuits., , and . ASYNC, page 206-215. IEEE Computer Society, (2003)