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Disambiguation of "Koike, Hanpei"

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XDXMOS: a novel technique for the double-gate MOSFETs logic circuits - to achieve high drive current and small input capacitance together.

, and . CICC, page 247-250. IEEE, (2005)

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Ursula Koike-Good

 

Other publications of authors with the same name

FPGAs with multidimensional mesh topology., , and . FPGA, page 223. ACM, (2006)Standard cell implementation of buskeeper PUF with symmetric inverters and neighboring cells for passing randomness tests., , and . GCCE, page 550-551. IEEE, (2015)Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity., , , , , , and . IEICE Trans. Inf. Syst., 87-D (8): 2004-2010 (2004)Fast Speculative Search Engine on the Highly Parallel Computer EM-X., , , , and . SIGIR, page 390. ACM, (1998)Fast Execution Mechanisms of Parallel Inference Engine PIE: PIEpelined Goal Rewriting and Goal Multicasting., and . LP, volume 264 of Lecture Notes in Computer Science, page 159-169. Springer, (1986)A Fleng Compiler for PIE64., , , and . IFIP PACT, volume A-50 of IFIP Transactions, page 257-266. North-Holland, (1994)A Cryogenic CMOS Current Integrator and Correlation Double Sampling Circuit for Spin Qubit Readout., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (12): 5220-5228 (December 2023)A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology., , , , , , , , , and 2 other author(s). IEICE Trans. Electron., 95-C (4): 686-695 (2012)Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA., , , , , , and . IEICE Trans. Inf. Syst., 90-D (12): 1947-1955 (2007)UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64., , and . FGCS, page 715-722. IOS Press, (1992)