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Runtime-assisted cache coherence deactivation in task parallel programs., , , , and . SC, page 35:1-35:12. IEEE / ACM, (2018)Dynamic Cache Partitioning Based on the MLP of Cache Misses., , , and . Trans. High Perform. Embed. Archit. Compil., (2011)CPU Accounting in CMP Processors., , , , , and . IEEE Comput. Archit. Lett., 8 (1): 17-20 (2009)Adaptive Power Shifting for Power-Constrained Heterogeneous Systems., , , , , , and . IEEE Trans. Computers, 72 (3): 627-640 (March 2023)On the use of many-core Marvell ThunderX2 processor for HPC workloads., , , and . J. Supercomput., 77 (4): 3315-3338 (2021)SafeSU: an Extended Statistics Unit for Multicore Timing Interference., , , , , , , and . ETS, page 1-4. IEEE, (2021)Evolutionary system for prediction and optimization of hardware architecture performance., , , , , , , and . IEEE Congress on Evolutionary Computation, page 1941-1948. IEEE, (2008)VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations., , , , , , , , and . HPCA, page 921-934. IEEE, (2021)Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs., , , , , , , , , and . DATE, page 628-631. IEEE, (2022)Evaluating Execution Time Predictability of Task-Based Programs on Multi-Core Processors., , , , and . Euro-Par Workshops (2), volume 8806 of Lecture Notes in Computer Science, page 218-229. Springer, (2014)