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High efficiency data access system architecture for deblocking filter supporting multiple video coding standards.

, , , , and . IEEE Trans. Consumer Electronics, 58 (2): 670-678 (2012)

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High efficiency data access system architecture for deblocking filter supporting multiple video coding standards., , , , and . IEEE Trans. Consumer Electronics, 58 (2): 670-678 (2012)Joint algorithm/code-level optimization of H.264 video decoder for mobile multimedia applications., , , , and . ICASSP, page 2189-2192. IEEE, (2008)A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation., , and . ISCAS, page 1569-1572. IEEE, (2007)Optimization of AVS-M Video Decoder for Real-time Implementation on Embedded RISC Processors., , and . IIH-MSP, page 98-101. IEEE Computer Society, (2009)A Verification-Aware Design Methodology for Thread Pipelining Parallelization., , , and . IEICE Trans. Inf. Syst., 95-D (10): 2505-2513 (2012)A low complexity multi-view video encoder exploiting B-frame characteristics., , , , and . APSIPA, page 1-4. IEEE, (2013)Real-Time 3D Depth Generation for Stereoscopic Video Applications with Thread-Level Superscalar-Pipeline Parallelization., , , and . J. Signal Process. Syst., 72 (1): 17-33 (2013)Optimization of VC-1/H.264/AVS Video Decoders on Embedded Processors., , , and . ITNG, page 1313-1318. IEEE Computer Society, (2009)3D depth map generation for embedded stereo applications., , , , and . VCIP, page 1-6. IEEE, (2012)A real-time parallel scalable video encoder for multimedia streaming systems., , , , and . VLSI-DAT, page 1-4. IEEE, (2013)