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Design methodology of multistage time-domain logic speculation circuits.

Y. Sun, Y. Liu, X. Wang, H. Xu, and H. Yang. ISCAS, page 1944-1947. IEEE, (2011)

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Yang Yang

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A "Near-the-Best" System-Level Design Methodology of Multi-Core H.264 Video Decoder Based on the Parallelized Multi-Core Simulator.B. Xia, F. Qiao, Z. Du, D. Zhu, and H. Yang. Journal of Circuits, Systems, and Computers, (2012)Increasing Compression Ratio of Low Complexity Compressive Sensing Video Encoder with Application-Aware Configurable Mechanism.S. Yu, F. Qiao, L. Luo, and H. Yang. CoRR, (2013)A Survey of FPGA Based Neural Network Accelerator.K. Guo, S. Zeng, J. Yu, Y. Wang, and H. Yang. CoRR, (2017)A Novel Reconfigurable Computing Architecture for Image Signal Processing Using Circuit-Switched NoC and Synchronous Dataflow Model.F. Li, F. Qiao, Q. Wei, and H. Yang. CoRR, (2013)Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.Y. Wang, Y. Liu, R. Luo, H. Yang, and H. Wang. ISLPED, page 238-243. ACM, (2006)Nonparametric Topic Modeling with Neural Inference.X. Ning, Y. Zheng, Z. Jiang, Y. Wang, H. Yang, and J. Huang. CoRR, (2018)Merging the interface: power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal computing system.B. Li, L. Xia, P. Gu, Y. Wang, and H. Yang. DAC, page 13:1-13:6. ACM, (2015)A low-complexity symbol-level differential detection scheme for IEEE 802.15.4 O-QPSK signals.C. Wang, Y. Liu, R. Luo, and H. Yang. WCSP, page 1-6. IEEE, (2012)Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation.Y. Wang, H. Luo, K. He, R. Luo, H. Yang, and Y. Xie. IEEE Trans. Dependable Secur. Comput., 8 (5): 756-769 (2011)14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse.J. Yue, Z. Yuan, X. Feng, Y. He, Z. Zhang, X. Si, R. Liu, M. Chang, X. Li, H. Yang and 1 other author(s). ISSCC, page 234-236. IEEE, (2020)

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Disambiguation of "Yang, Huazhong"

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Design methodology of multistage time-domain logic speculation circuits.

Please choose a person to relate this publication to

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yang, Huazhong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Design methodology of multistage time-domain logic speculation circuits.

Please choose a person to relate this publication to

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Other publications of authors with the same name

Disambiguation

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APA
Chicago
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Design methodology of multistage time-domain logic speculation circuits.