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Disambiguation of "Tamura, Hirotaka"

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A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS.

, , , , , , and . CICC, page 1-4. IEEE, (2010)

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Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

 

Other publications of authors with the same name

Charge recycling for power reduction in FPGA interconnect., , and . FPL, page 1-8. IEEE, (2013)A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process., , , , , , , , , and . CICC, page 131-134. IEEE, (2005)Jitter injection for on-chip jitter measurement in PI-based CDRs., , , and . CICC, page 1-4. IEEE, (2017)A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE., , , , and . CICC, page 1-4. IEEE, (2014)An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection., , , , and . CICC, page 1-8. IEEE, (2013)Optimizing effective interconnect capacitance for FPGA power reduction., , and . FPGA, page 11-20. ACM, (2014)A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS., , , , , , , , , and 5 other author(s). ISSCC, page 168-169. IEEE, (2010)A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology., , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2456-2462 (2010)An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset"., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (7): 2129-2138 (2014)Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (5): 1306-1315 (2008)