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Independent N and P process monitors for body bias based process corner correction.

, , , , and . CICC, page 1-4. IEEE, (2014)

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Mathematical Machines and Integrated Stem: An Intersubjective Constructionist Approach., , , and . CSEDU (Selected Papers), volume 510 of Communications in Computer and Information Science, page 272-288. Springer, (2014)SpikeSim: An End-to-End Compute-in-Memory Hardware Evaluation Tool for Benchmarking Spiking Neural Networks., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (11): 3815-3828 (November 2023)Integrated STEM in Elementary Grades Using Distributed Agent-based Computation., , and . CSEDU (2), page 67-78. SciTePress, (2014)COIN: Communication-Aware In-Memory Acceleration for Graph Convolutional Networks., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (2): 472-485 (2022)A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 10 (3): 362-375 (2020)SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks., , , , , , and . CoRR, (2021)Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation., , , , , , , and . DAC, page 1-6. IEEE, (2020)Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches., , , , , and . CoRR, (2019)Artificial intelligence in clinical medicine: catalyzing a sustainable global healthcare paradigm., , , , , , and . Frontiers Artif. Intell., (February 2023)Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture., , , , , , , and . ICCAD, page 8:1-8:9. ACM, (2022)