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Functional units with conditional input/output behavior in VLIW processors.

, , , and . DATE, page 822. IEEE Computer Society, (2001)

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Mpeg2 Video Encoding in Consumer Electronics., , , , and . VLSI Signal Processing, 17 (2-3): 241-253 (1997)Allocation of multiport memories for hierarchical data stream., , , and . ICCAD, page 728-735. IEEE Computer Society / ACM, (1993)Efficient timing constraint derivation for optimal retiming high speed processing units., , , , and . HLSS, page 48-53. ACM, (1994)Multidimensional Periodic Scheduling Model and Complexity., , , , and . Euro-Par, Vol. II, volume 1124 of Lecture Notes in Computer Science, page 226-235. Springer, (1996)PHIDEO: a silicon compiler for high speed algorithms., , , , , , and . EURO-DAC, page 436-441. EEE Computer Society, (1991)Scheduling Coarse-Grain Operations for VLIW Processors., , and . ISSS, page 47-54. ACM / IEEE Computer Society, (2000)PHIDEO: High-level synthesis for high throughput applications., , , and . VLSI Signal Processing, 9 (1-2): 89-104 (1995)Hierarchical Retiming Including Pipelining., , , , and . VLSI, volume A-1 of IFIP Transactions, page 451-460. North-Holland, (1991)HW-SW Co-Design and Verification of a Multi-Standard Video and Image Codec., , , , , , and . ISQED, page 393-398. IEEE Computer Society, (2001)Power-efficient layered turbo decoder processor., , , , , , and . DATE, page 246-251. IEEE Computer Society, (2001)