Author of the publication

Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going.

, , , , , , , and . ACM Comput. Surv., 52 (2): 40:1-40:39 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Honeycomb: ordered key-value store acceleration on an FPGA-based SmartNIC., , , , , , , , and . CoRR, (2023)Reconfigurable Acceleration of Short Read Mapping with Biological Consideration., , , and . FPGA, page 229-239. ACM, (2021)High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform., , , , , , , , and . ReConFig, page 1-6. IEEE, (2016)ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development., , and . FPGA, page 189-198. ACM, (2018)Investigating the Feasibility of FPGA-based Network Switches., , , , and . ASAP, page 218-226. IEEE, (2019)Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network., , , , , , , , and . IEEE Trans. Neural Networks Learn. Syst., 33 (7): 2853-2866 (2022)A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA., , , , , , , and . FPT, page 14-21. IEEE, (2018)Towards FPGA-assisted spark: An SVM training acceleration case study., , , and . ReConFig, page 1-6. IEEE, (2016)Memory-Efficient Architecture for Accelerating Generative Networks on FPGA., , , , , , , and . FPT, page 30-37. IEEE, (2018)Honeycomb: Ordered Key-Value Store Acceleration on an FPGA-Based SmartNIC., , , , , , , , and . IEEE Trans. Computers, 73 (3): 857-871 (March 2024)