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Synergistic integration of code encryption and compression in embedded systems.

, , , and . ACM Great Lakes Symposium on VLSI, page 363-368. ACM, (2012)

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Synergistic integration of dynamic cache reconfiguration and code compression in embedded systems., , and . IGCC, page 1-8. IEEE Computer Society, (2011)Postsilicon Trace Signal Selection Using Machine Learning Techniques., , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (2): 570-580 (2017)Feature-Based Signal Selection for Post-Silicon Debug Using Machine Learning., and . IEEE Trans. Emerg. Top. Comput., 8 (4): 907-915 (2020)Efficient Peak Power Estimation Using Probabilistic Cost-Benefit Analysis., , and . VLSID, page 369-374. IEEE Computer Society, (2015)Efficient Signal Selection Using Fine-grained Combination of Scan and Trace Buffers., and . VLSI Design, page 308-313. IEEE Computer Society, (2013)Compression-aware dynamic cache reconfiguration for embedded systems., , and . Sustain. Comput. Informatics Syst., 2 (2): 71-80 (2012)Efficient trace signal selection using augmentation and ILP techniques., , and . ISQED, page 148-155. IEEE, (2014)Efficient Selection of Trace and Scan Signals for Post-Silicon Debug., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 313-323 (2016)Scalable trace signal selection using machine learning., , and . ICCD, page 384-389. IEEE Computer Society, (2013)Synergistic integration of code encryption and compression in embedded systems., , , and . ACM Great Lakes Symposium on VLSI, page 363-368. ACM, (2012)