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Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C-V Technique., , and . IEEE Trans. Instrumentation and Measurement, 61 (7): 1979-1990 (2012)3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot., , , , , , , , and . Proc. IEEE, 97 (1): 96-107 (2009)Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC-TSI)., , , , , , , , , and . IEEE Des. Test, 32 (4): 23-31 (2015)Design issues and considerations for low-cost 3D TSV IC technology., , , , , , , , , and 24 other author(s). ISSCC, page 148-149. IEEE, (2010)3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)., , , , , , , , , and 3 other author(s). 3DIC, page 1-5. IEEE, (2009)Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions., , , , , , , , , and 8 other author(s). CICC, page 1-4. IEEE, (2010)Design Issues and Considerations for Low-Cost 3-D TSV IC Technology., , , , , , , , , and 27 other author(s). IEEE J. Solid State Circuits, 46 (1): 293-307 (2011)