( en | de | ru )

 

Disambiguation of "Zhuge, Qingfeng"

Author of the publication

copydeleteadd this publication to your clipboard
An Integrated Framework of Design Optimization and Space Minimization for DSP applications.

, , and . ISCAS (5), page 601-604. IEEE, (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Zhuge, Qingfeng
add a person with the name Zhuge, Qingfeng
 

Other publications of authors with the same name

Towards the design of efficient hash-based indexing scheme for growing databases on non-volatile memory., , , , , and . Future Gener. Comput. Syst., (2020)Algorithms for Optimally Arranging Multicore Memory Structures., , , , and . EURASIP J. Embed. Syst., (2010)Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors., , , and . IJHPCN, 1 (1/2/3): 4-16 (2004)An Integrated Framework of Design Optimization and Space Minimization for DSP applications., , and . ISCAS (5), page 601-604. IEEE, (2003)Performance optimization of multiple memory architectures for DSP., , and . ISCAS (5), page 469-472. IEEE, (2002)Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors., , , , and . ACM Trans. Embed. Comput. Syst., 13 (4): 79:1-79:25 (2014)Application-Specific Wear Leveling for Extending Lifetime of Phase Change Memory in Embedded Systems., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (10): 1450-1462 (2014)Data Placement and Duplication for Embedded Multicore Systems With Scratch Pad Memory., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (6): 809-817 (2013)Efficient Multi-Grained Wear Leveling for Inodes of Persistent Memory File Systems., , , , , , , and . DAC, page 1-6. IEEE, (2020)General loop fusion technique for nested loops considering timing and code size., , , and . CASES, page 190-201. ACM, (2004)