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An Integrated Framework of Design Optimization and Space Minimization for DSP applications.

, , and . ISCAS (5), page 601-604. IEEE, (2003)

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Communication Scheduling With Re-Routing Based On Static And Hybrid Techniques., , and . Journal of Circuits, Systems, and Computers, 13 (5): 1039-1064 (2004)Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping., , and . VLSI Signal Processing, 47 (2): 153-167 (2007)Performance optimization of multiple memory architectures for DSP., , and . ISCAS (5), page 469-472. IEEE, (2002)Partitioning and Retiming of Multi-Dimensional Systems., , and . ISCAS, page 227-230. IEEE, (1994)An Integrated Framework of Design Optimization and Space Minimization for DSP applications., , and . ISCAS (5), page 601-604. IEEE, (2003)A novel multiplexer-based low-power full adder., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 51-II (7): 345-348 (2004)An Empirical Study of NVM-based File System., , , , , and . NVMSA, page 1-6. IEEE, (2021)Hardware/Software Co-Exploration of Neural Architectures., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 4805-4815 (2020)Rapid recovery of program execution under power failures for embedded systems with NVM., , , , and . Microprocess. Microsystems, (2023)Reconfigurability and reliability of systolic/wavefront arrays., and . ICASSP, page 1001-1004. IEEE Computer Society, (1991)