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Improving performance of loops on DIAM-based VLIW architectures., , , and . LCTES, page 135-144. ACM, (2014)A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (7): 1018-1027 (2010)Training-Free Stuck-At Fault Mitigation for ReRAM-Based Deep Learning Accelerators., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2174-2186 (July 2023)Evaluator-executor transformation for efficient pipelining of loops with conditionals., , and . ACM Trans. Archit. Code Optim., 10 (4): 62:1-62:23 (2013)Improving performance of nested loops on reconfigurable array processors., , , and . ACM Trans. Archit. Code Optim., 8 (4): 32:1-32:23 (2012)Memory access optimization in compilation for coarse-grained reconfigurable architectures., , , and . ACM Trans. Design Autom. Electr. Syst., 16 (4): 42:1-42:27 (2011)RRNet: Repetition-Reduction Network for Energy Efficient Decoder of Depth Estimation., , , and . CoRR, (2019)Accurate Prediction of ReRAM Crossbar Performance Under I-V Nonlinearity and IR Drop., , , , and . ICCD, page 9-16. IEEE, (2022)SparTANN: sparse training accelerator for neural networks with threshold-based sparsification., , and . ISLPED, page 211-216. ACM, (2020)Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (8): 2799-2802 (2016)