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The SIMD accelerator for business analytics on the IBM z13.

, , , , , и . IBM J. Res. Dev., (2015)

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Eric W M Roosenboom

Hauke Erichsen

Ull Erich

Gerda Erich

Badrian Erich

 

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FPU Implementations with Denormalized Numbers., , и . IEEE Trans. Computers, 54 (7): 825-836 (2005)CMOS floating-point unit for the S/390 Parallel Enterprise Server G4., , и . IBM J. Res. Dev., 41 (4&5): 475-488 (1997)The SIMD accelerator for business analytics on the IBM z13., , , , , и . IBM J. Res. Dev., (2015)A General Proof for Overlapped Multiple-Bit Scanning Multiplications., , и . IEEE Trans. Computers, 38 (2): 172-183 (1989)A Decimal Floating-Point Specification., , , и . IEEE Symposium on Computer Arithmetic, стр. 147-154. IEEE Computer Society, (2001)Decimal Multiplication with Efficient Partial Product Generation., , и . IEEE Symposium on Computer Arithmetic, стр. 21-28. IEEE Computer Society, (2005)ATPG Aspects of FSM Verification., , , , , и . ICCAD, стр. 134-137. IEEE Computer Society, (1990)On optimal extraction of combinational logic and don't care sets from hardware description languages., , , , и . ICCAD, стр. 308-311. IEEE Computer Society, (1989)Hard-Wired Multipliers with Encoded Partial Products., , и . IEEE Trans. Computers, 40 (11): 1181-1197 (1991)Correction: IEEE Transactions on Computers 42(1): 127 (1993).A Radix-8 CMOS S/390 Multiplier., , и . IEEE Symposium on Computer Arithmetic, стр. 2-9. IEEE Computer Society, (1997)