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A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS., , , , and . ISSCC, page 296-297. IEEE, (2010)Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 51 (7): 1579-1592 (2016)A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS., , and . IEEE J. Solid State Circuits, 47 (12): 2880-2887 (2012)The Potential of FinFETs for Analog and RF Circuit Applications., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (11): 2541-2551 (2007)A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC., , , , , and . ESSCIRC, page 215-218. IEEE, (2014)A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET., , , , , , , , , and 10 other author(s). VLSI Circuits, page 99-100. IEEE, (2018)A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS., , , , and . ISSCC, page 252-253. IEEE, (2008)A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range., , , , and . ISSCC, page 470-472. IEEE, (2012)A programmable RFSoC in 16nm FinFET technology for wideband communications., , , , , , , , , and 5 other author(s). A-SSCC, page 1-4. IEEE, (2017)A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS., , , and . VLSIC, page 1-2. IEEE, (2014)