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Disambiguation of "Jarwala, Najmi T."

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Hardware-Software Co-Design for Test: It's the Last Straw!

, , , , , , and . VTS, page 506-507. IEEE Computer Society, (1996)

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Other publications of authors with the same name

A structured approach to board-level BIST using the boundary-scan master., and . Microprocess. Microsystems, 17 (5): 289-297 (1993)TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's., and . IEEE Trans. Computers, 37 (10): 1235-1250 (1988)Lessons Learned from Practical Applications of BIST/B-S Technology., , , and . Asian Test Symposium, page 251-257. IEEE Computer Society, (1996)Designing "Dual-Personality" IEEE 1149.1-Compliant Multi-Chip Modules.. ITC, page 446-455. IEEE Computer Society, (1994)A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects., and . ITC, page 63-70. IEEE Computer Society, (1989)Hardware-Software Co-Design for Test: It's the Last Straw!, , , , , , and . VTS, page 506-507. IEEE Computer Society, (1996)Built-In Self-Test: Assuring System Integrity., , , and . Computer, 29 (11): 39-45 (1996)Achieving Board-Level BIST Using the Boundary-Scan Master., and . ITC, page 649-658. IEEE Computer Society, (1991)The boundary-scan master: target applications and functional requirements., and . ITC, page 311-315. IEEE Computer Society, (1990)A Framework for Boundary-Scan Based System Test Diagnosis., , , and . ITC, page 993-998. IEEE Computer Society, (1992)