( en | de | ru )

 

Disambiguation of "Rajski, Janusz"

Author of the publication

copydeleteadd this publication to your clipboard
Hardware-Software Co-Design for Test: It's the Last Straw!

, , , , , , and . VTS, page 506-507. IEEE Computer Society, (1996)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Janusz Gatniejewski

Janusz Panzer

Janusz Rat

Janusz Surzykiewicz

Janusz Bogdanowicz

 

Other publications of authors with the same name

Embedded deterministic test points for compact cell-aware tests., , , , , , , , , and . ITC, page 1-8. IEEE, (2015)High Performance Dense Ring Generators., , , and . IEEE Trans. Computers, 55 (1): 83-87 (2006)Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits., and . ITC, page 473-482. IEEE Computer Society, (1991)On Using Implied Values in EDT-based Test Compression., , , , and . DAC, page 11:1-11:6. ACM, (2014)Built-In Self-Test for Systems on Silicon., , and . VLSI Design, page 609-610. IEEE Computer Society, (1999)On Linear Dependencies in Subspaces of LFSR-Generated Sequences., and . IEEE Trans. Computers, 45 (10): 1212-1216 (1996)Self-test methodology for at-speed test of crosstalk in chip interconnects., , and . DAC, page 619-624. ACM, (2000)EDT Bandwidth Management in SoC Designs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (12): 1894-1907 (2012)Embedded deterministic test., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (5): 776-792 (2004)Logic BIST With Capture-Per-Clock Hybrid Test Points., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (6): 1028-1041 (2019)