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Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution.

Y. Lu, L. Liu, Y. Deng, J. Weng, Z. Li, C. Deng, and S. Wei. DAC, page 71:1-71:6. ACM, (2017)

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Shaojun Lu

Shaojun Tong

Wei Wei

Other publications of authors with the same name

A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System.M. Zhu, L. Liu, S. Yin, C. Yin, and S. Wei. IEICE Trans. Inf. Syst., 93-D (12): 3202-3210 (2010)Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors.H. Luo, S. Wei, D. Chen, and D. Guo. J. Parallel Distributed Comput., 74 (9): 2818-2830 (2014)Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture.Y. Wang, L. Liu, S. Yin, M. Zhu, P. Cao, J. Yang, and S. Wei. Sci. China Inf. Sci., 56 (11): 1-20 (2013)Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system.L. Liu, Y. Chen, S. Yin, L. Zhou, H. Yuan, and S. Wei. Sci. China Inf. Sci., 57 (8): 1-14 (2014)Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures.S. Yin, X. Yao, D. Liu, L. Liu, and S. Wei. IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1895-1908 (2016)Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms.P. Ouyang, S. Yin, L. Liu, and S. Wei. IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 3085-3098 (2015)Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution.Y. Lu, L. Liu, Y. Deng, J. Weng, Z. Li, C. Deng, and S. Wei. DAC, page 71:1-71:6. ACM, (2017)Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD.B. Xu, S. Yin, L. Liu, and S. Wei. IEICE Trans. Inf. Syst., 98-D (2): 243-251 (2015)An Ultra-Low Power Binarized Convolutional Neural Network-Based Speech Recognition Processor With On-Chip Self-Learning.S. Zheng, P. Ouyang, D. Song, X. Li, L. Liu, S. Wei, and S. Yin. IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (12): 4648-4661 (2019)PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC.C. Deng, L. Liu, Y. Liu, S. Yin, and S. Wei. IEEE Trans. Circuits Syst. II Express Briefs, 64-II (5): 540-544 (2017)

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Disambiguation of "Wei, Shaojun"

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Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution.

Please choose a person to relate this publication to

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wei, Shaojun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution.

Please choose a person to relate this publication to

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution.