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Disambiguation of "Batude, Perrine"

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CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.

, , , , , , , and . ASP-DAC, page 336-343. IEEE, (2011)

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Perrine Marthelot

Perrine Debaene

Perrine Broy

Perrine Chancerel

Perrine Pittet

 

Other publications of authors with the same name

3D FPGA using high-density interconnect Monolithic Integration., , , , and . DATE, page 1-4. European Design and Automation Association, (2014)Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices., , , , , , , , , and 5 other author(s). ESSDERC, page 144-147. IEEE, (2017)Intermediate BEOL process influence on power and performance for 3DVLSI., , , , , , , and . 3DIC, page TS1.3.1-TS1.3.5. IEEE, (2015)Impact of intermediate BEOL technology on standard cell performances of 3D VLSI., , , , , , , , , and 3 other author(s). ESSDERC, page 218-221. IEEE, (2016)A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit., , , , , , , , and . ICICDT, page 141-144. IEEE, (2018)Analytical modeling of parasitics in monolithically integrated 3D inverters., , , and . ICICDT, page 1-4. IEEE, (2012)FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration., , , , , , , , , and 6 other author(s). ESSDERC, page 110-113. IEEE, (2014)CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits., , , , , , , and . ASP-DAC, page 336-343. IEEE, (2011)Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells., , , , , , , , , and 2 other author(s). ISVLSI, page 539-544. IEEE Computer Society, (2017)Recent advances in 3D VLSI integration., , , , , , , , , and 7 other author(s). ICICDT, page 1-4. IEEE, (2016)