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CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.

S. Bobba, A. Chakraborty, O. Thomas, P. Batude, T. Ernst, O. Faynot, D. Pan, and G. Micheli. ASP-DAC, page 336-343. IEEE, (2011)

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Thomas Olivier

Eduard Olivier

Other publications of authors with the same name

Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology.O. Thomas, M. Reyboz, and M. Belleville. ISCAS, page 2778-2781. IEEE, (2007)Ultra low voltage design considerations of SOI SRAM memory cells.O. Thomas, and A. Amara. ISCAS (4), page 4094-4097. IEEE, (2005)Design challenges for nano-scale devices.M. Belleville, O. Thomas, A. Valentian, and F. Clermidy. ESSDERC, page 69-72. IEEE, (2012)Thermo-mechanical study of a 2.5D passive silicon interposer technology: Experimental, numerical and In-Situ stress sensors developments.B. Vianne, P. Bar, V. Fiori, S. Petitdidier, N. Chevrier, S. Gallois-Garreignot, A. Farcy, P. Chausse, S. Escoubas, N. Hotellier and 1 other author(s). 3DIC, page 1-7. IEEE, (2013)ExPACO: detection of an extended pattern under nonstationary correlated noise by patch covariance modeling.O. Flasseur, L. Denis, É. Thiébaut, T. Olivier, and C. Fournier. EUSIPCO, page 1-5. IEEE, (2019)Design, Fabrication and Dynamic Testing of Insect-Inspired Nano Air Vehicles.S. Grondel, D. Faux, M. de la Bigne, A. Itawi, M. Zwingelstein, S. Ghenna, C. Soyer, E. Cattan, and O. Thomas. MIXDES, page 17-22. IEEE, (2023)Resistive memories: Which applications?F. Clermidy, N. Jovanovic, S. Onkaraiah, H. Oucheikh, O. Thomas, O. Turkyilmaz, E. Vianello, J. Portal, and M. Bocquet. DATE, page 1-6. European Design and Automation Association, (2014)Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI.K. Akyel, L. Ciampolini, O. Thomas, D. Turgis, and G. Ghibaudo. ESSDERC, page 94-97. IEEE, (2014)OxRAM-based non volatile flip-flop in 28nm FDSOI.N. Jovanovic, O. Thomas, E. Vianello, J. Portal, B. Nikolic, and L. Naviner. NEWCAS, page 141-144. IEEE, (2014)Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology.P. Flatresse, B. Giraud, J. Noel, B. Pelloux-Prayer, F. Giner, D. Arora, F. Arnaud, N. Planes, J. Coz, O. Thomas and 4 other author(s). ISSCC, page 424-425. IEEE, (2013)

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Disambiguation of "Thomas, Olivier"

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CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.

Please choose a person to relate this publication to

Thomas Olivier

Thomas Olivier

Thomas Olivier

Thomas Olivier

Eduard Olivier

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Thomas, Olivier"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.

Please choose a person to relate this publication to

Thomas Olivier

Thomas Olivier

Thomas Olivier

Thomas Olivier

Eduard Olivier

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.