( en | de | ru )

 

Disambiguation of "Fujiwara, Hideo"

Author of the publication

copydeleteadd this publication to your clipboard
Test sequence compaction methods for acyclic sequential circuits using a time expansion model.

, , , and . Syst. Comput. Jpn., 33 (10): 105-115 (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Esther Fujiwara

Hideo Baba

Hideo Ohashi

Hideo Andreas Baba

Hideo Ikezawa-Hanada

 

Other publications of authors with the same name

The Complexity of Fault Detection Problems for Combinational Logic Circuits., and . IEEE Trans. Computers, 31 (6): 555-560 (1982)New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency., , and . J. Electron. Test., 20 (3): 315-323 (2004)Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption., , and . J. Electron. Test., 18 (1): 55-62 (2002)Handling the pin overhead problem of DFTs for high-quality and at-speed tests., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (9): 1105-1113 (2002)SPIRIT: a highly robust combinational test generation algorithm., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (12): 1446-1458 (2002)Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints., , , , , and . J. Electron. Test., 28 (4): 511-521 (2012)A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings., , , and . J. Parallel Distributed Comput., 62 (5): 865-884 (2002)A cost optimal parallel algorithm for weighted distance transforms., , , and . Parallel Comput., 25 (4): 405-416 (1999)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)System-on-chip test scheduling with reconfigurable core wrappers., and . IEEE Trans. Very Large Scale Integr. Syst., 14 (3): 305-309 (2006)