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Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductors.

D. Linten, X. Sun, S. Thijs, M. Natarajan, A. Mercha, G. Carchon, P. Wambacq, T. Nakaie, and S. Decoutere. CICC, page 497-500. IEEE, (2005)

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Claudia Simone Linten

Dimitri Chronopulos

Thomas Dimitri

Dimitri Barski

Dimitri Hartl

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ESD protection diodes in optical interposer technology.R. Boschke, G. Groeseneken, M. Scholz, S. Chen, G. Hellings, P. Verheyen, and D. Linten. ICICDT, page 1-4. IEEE, (2015)Reliability challenges in Forksheet Devices: (Invited Paper).E. Bury, M. Vandemaele, J. Franco, A. Chasin, S. Tyaginov, A. Vandooren, R. Ritzenthaler, H. Mertens, J. Diaz-Fortuny, N. Horiguchi and 2 other author(s). IRPS, page 1-8. IEEE, (2023)Physics-based device aging modelling framework for accurate circuit reliability assessment.Z. Wu, J. Franco, B. Truijen, P. Roussel, S. Tyaginov, M. Vandemaele, E. Bury, G. Groeseneken, D. Linten, and B. Kaczer. IRPS, page 1-6. IEEE, (2021)ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology.M. Simicic, G. Hellings, S. Chen, N. Horiguchi, and D. Linten. ESSDERC, page 194-197. IEEE, (2018)Processing active devices on Si interposer and impact on cost.D. Velenis, M. Detalle, G. Hellings, M. Scholz, E. Marinissen, G. der Plas, A. Manna, A. Miller, D. Linten, and E. Beyne. 3DIC, page TS11.2.1-TS11.2.4. IEEE, (2015)Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.B. O'Sullivan, R. Ritzenthaler, G. Rzepa, Z. Wu, E. Litta, O. Richard, T. Conard, V. Machkaoutsan, P. Fazan, C. Kim and 6 other author(s). IRPS, page 1-8. IEEE, (2019)Self-heating-aware CMOS reliability characterization using degradation maps.E. Bury, A. Chasin, B. Kaczer, K. Chuang, J. Franco, M. Simicic, P. Weckx, and D. Linten. IRPS, page 2. IEEE, (2018)Impact of slow and fast oxide traps on In0.53Ga0.47As device operation studied using CET maps.V. Putcha, J. Franco, A. Vais, B. Kaczer, S. Sioncke, D. Linten, and G. Groeseneken. IRPS, page 5. IEEE, (2018)Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown.B. O'Sullivan, S. Beek, P. Roussel, S. Rao, W. Kim, S. Couet, J. Swerts, F. Yasin, D. Crotti, D. Linten and 1 other author(s). IRPS, page 5-1. IEEE, (2018)A Pragmatic Model to Predict Future Device Aging.J. Brown, K. Tok, R. Gao, Z. Ji, W. Zhang, J. Marsland, T. Chiarella, J. Franco, B. Kaczer, D. Linten and 1 other author(s). IEEE Access, (2023)

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Disambiguation of "Linten, Dimitri"

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Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductors.

Please choose a person to relate this publication to

Claudia Simone Linten

Dimitri Chronopulos

Thomas Dimitri

Dimitri Barski

Dimitri Hartl

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Linten, Dimitri"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductors.

Please choose a person to relate this publication to

Claudia Simone Linten

Dimitri Chronopulos

Thomas Dimitri

Dimitri Barski

Dimitri Hartl

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
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Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductors.